Partial Reconfiguration with FPGA
Learn about the complete Partial Reconfiguration Flow with Xilinx VIVADO and FPGA
Ratings 3.70 / 5.00
What You Will Learn!
- Partial Reconfiguration Design Flow
- Xilinx VIVADO tool and FPGA devices for Partial Reconfiguration Flow
- Debugging the PR Design with ILA and VIO
- Using PR Controller with VIVADO IP platform and FPGA
Description
This course covers the basics of "Partial Reconfiguration (PR)" flow with Xilinx VIVADO tool and FPGA. We have followed the standard syllabus on this training, so the enthusiast who want to learn will get in depth knowledge and skills on the "Partial Reconfiguration". PR flow is necessary when there is larger design and need to fit on the specific series of FPGA. PR flow is followed on the Xilinx as well as Intel-Altera based design tools and FPGA.
This are the major points which covered on this course:
Partial Reconfiguration flow with Xilinx VIVADO and FPGA [7 series, Ultrascale and Ultrascale+ FPGAs]
Using Debugging method [using ILA and VIO] on Partial Reconfiguration flow
Designing PR flow with Partial Reconfigurable Controller
PR flow with MicroBlaze
BitStream Relocation-overview
Who Should Attend!
- FPGA Design Enthusiast
- Electrical Engineering and Computer Science Student
![Practical FPGA project design [UART]](https://img-c.udemycdn.com/course/50x50/4315538_fe38.jpg "Practical FPGA project design [UART]")