Questasim ile FPGA Simulasyon /FPGA Verification with Questa
FPGA Dogrulama, TCL , Batch ve GUI Mode (Verification) / FPGA Verification, TCL, Batch and GUI mode
Ratings 5.00 / 5.00
What You Will Learn!
- Turkish and English Explanations are written below.
- Questasim ve Modelsim karsilastirilmasi / Comparison between Questasim and Modelsim
- Manuel olarak Modelsim ve Questasim’de simulasyon kosturma (GUI) / Running simulation manually on Modelsim and Questasim (GUI)
- Test Types / Code Coverage/ Functional Coverage
- Questasim uzerinde Code coverage uygulamasi / Code coverage application on Questasim
- Functional Coverage hakkinda bilgiler, referanslar/ Information and references about Functional Coverage
- Vivado ile Questasim simulasyonu kosturma / Running Questasim simulation with Vivado
- Window & Linux environment variable set etme, TCL Referans / Window & Linux environment variable setting, TCL Reference
- Questasim ile TCL komutlari kosturulmasi (Batch mode) / Running TCL commands with Questasim (Batch mode)
- Questasim ile ornek uygulamalar (SystemVerilog) / Example applications with Questasim (SystemVerilog)
Description
Information: Auto Generated English, Spanish, Russian, Arabic and Hindi subtitles are added.
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// TURKISH
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Yeni bir Udemy kursu!
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Kurs: Questasim ile FPGA Simulasyonu
Not: Bu kursun amaci Questasim ile FPGA tasariminin dogrulanmasidir.
Dolayisiyla kursu almadan once Verilog ve SystemVerilog bilinmesi iyi olacaktir.
Aksi taktirde kurs sizin icin verimli olmayacaktir.
Kursa baslamadan once bilgisayarinizda Vivado ve Questasim kurulu olmalidir.
Ders 1: Questasim ve Modelsim karsilastirilmasi
Ders 2: Manuel olarak Modelsim/Questasim’de simulasyon kosturma (GUI)
Ders 3: Test Types / Code Coverage – Functional Coverage nedir?
Ders 4: Questasim uzerinde Code coverage uygulamasi
Ders 5: Functional Coverage hakkinda bilgiler, referanslar
Ders 6: Vivado ile Questasim simulasyonu kosturma
Ders 7: Window & Linux environment variable set etme, TCL Referans
Ders 8: Questasim ile TCL komutlari kosturulmasi (Batch mode)
Ders 9: Questasim ile ornek uygulamalar (SystemVerilog)
Kursa ait butun slaytlar ilk video dersinde yer almaktadir. Her video icin gerekli materyaller kurs videolarina eklenmistir.
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// ENGLISH
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Note: The primary objective of this course is to verify FPGA designs using Questasim. Consequently, having prior knowledge of Verilog and SystemVerilog is highly recommended before enrolling in this course. Without this prerequisite, the course may not be as beneficial. Furthermore, it is essential to ensure that you have both Vivado and Questasim installed on your computer before commencing the course.
Lesson 1: Comparison of Questasim and Modelsim
Lesson 2: Running a simulation manually in Modelsim/Questasim (GUI)
Lesson 3: Test Types / Code Coverage – What is Functional Coverage?
Lesson 4: Code coverage application on Questasim
Lesson 5: Information and references about Functional Coverage
Lesson 6: Running a Questasim simulation with Vivado
Lesson 7: Setting Window & Linux environment variables, TCL Reference
Lesson 8: Executing TCL commands with Questasim (Batch mode)
Lesson 9: Example applications with Questasim (SystemVerilog)
All slides of the course are included in the first video lesson. The necessary materials for each video have been added to the course videos.
Who Should Attend!
- Turkish: Bu kurs FPGA tasarimini ogrenmis, verilog ve systemverilog ile tasarim yapip simulasyon kosturmus kisiler icindir.
- English: This course is intended for individuals who already possess knowledge of FPGA design and are proficient in conducting simulations using Verilog and SystemVerilog.