RISC-V Interrupts & Platform Level Interrupt Controller
Write RISC-V assembly code to configure GPIO, PLIC and Core CSRs to generate GPIO interrupt and blink blue LED on board
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What You Will Learn!
- Understand privilege levels, traps and control and status registers
- Platform Level Interrupt Controller Specification
- Sample implementation of PLIC module on FE310 SoC
- Writing assembly code, compiling, linking with GNU tools and debugging with OpenOCD and GDB
- Demonstration of interrupt generation & handling in RISC-V assembly
Description
Interrupts in RISC-V are governed by standards and specification. Each RISC-V core's interrupt generation and handling process should be compliant to the specification.
This course discusses the following:
a. Privilege Levels in RISC-V
b. Traps in RISC-V
c. Platform Level Interrupt Controller (PLIC) Specification
d. Compares PLIC Implementation on FE310 SoC to Spec
e. Control and Status Registers (CSRs)
f. Instructions to read and write CSRs in RISC-V
g. Configuring GPIO peripheral in FE310 SoC
h. Configuring PLIC to allow GPIO interrupt
i. Configure MIE & MSTATUS CSRs on the core to enable machine mode interrupts and machine mode external interrupts
j. Installation of GNU tools (compilers, OpenOCD)
k. Test application in assembly to blink blue LED on Hifive1-Rev B board.
Students who enrol would be taken through a journey starting from basics of what are interrupts, exceptions and traps in RISC-V, followed by PLIC standard discussing the parameters, how to configure those parameters on PLIC to generate interrupt and claiming and completing the interrupt handling process and finally on writing an test application to blink LED.
The major exercise and focus on this course is on writing RISC-V assembly code, assembling & linking with GNU tools, generating ELF, and programming it on Hifive1-RevB board to blink blue LED on board.
Who Should Attend!
- Embedded system developers and RISC-V enthusiasts