VSD - Clock Tree Synthesis - Part 1
VLSI - Building a chip is like building a city!!
Ratings 4.31 / 5.00
What You Will Learn!
- CTS Quality Checks (Skew, Power, Latency, etc.)
- H-Tree
- Quality Check of H-Tree
- Clock Tree Buffering
- Buffered H-Tree
- H-Tree with uneven spread of Flops
- Advanced H-Tree for Million Flops
- Power Aware CTS (clock gating)
- Static Timing Analysis with Clock Tree
Description
Clock Tree Networks are Pillars and Columns of a Chip.
With these series of lectures, we have explored on-site concepts applied in VLSI industry. It is a One-Stop-Shop to understand industrial VLSI circuits.
The videos will develop an analytical approach to tackle technical challenges while building Clock Tree.
Who Should Attend!
- Individuals keen to learn about VLSI and Chip World
